Introduction

High-Performance Stackable SBC

Mixtile Blade 3 is a low-cost, low-power single-board computer (SBC) powered by the cutting-edge, 8-nanometer Rockchip RK3588 CPU. This power-efficient chipset makes Blade 3 ideal for quick development, AI-application prototyping, and edge computing. You can easily scale your deployment by clustering multiple Blade 3 boards together via the four-lane PCIe Gen3 port. This enables flexible, high-performance edge computing while maintaining a minimal carbon footprint.

Blade 3 Case is designed specifically for the needs and functionality of the Mixtile Blade 3. Integrating M.2 NVMe SSD support, this case has built-in fans for heat dissipation.

Figure 1. Mixtile Blade 3
Figure 2. Mixtile Blade 3 Case

Highlights

  • Strong scalability and wide applications

The mini PCIe interface and 30-pin GPIO header allow for easy expansion. The U.2 edge connector provides 12 V power, PCIe Gen 3.0 x 4, and SATA signals to interface with other Mixtile boards and build clusters. This makes Mixtile Blade 3 ideal for AI, edge computing, and image data processing applications requiring high bandwidth and scalability.

  • Rich display interfaces, up to 8K video decoding

The HDMI 2.1 output port enables up to 8K@60fps display, while the HDMI 2.0 input port allows for up to 4K@60fps capture. Two 1.4a DisplayPorts over Type-C provide additional display connectivity at up to 8K@30fps. For video input, the 4-lane MIPI-CSI interface is included.

Powerful H.265/VP9 hardware decoding up to 8K@60fps and H.264/H.265 encoding up to 8K@30fps enables real-time video processing on the board.

  • Wide range of OS compatibility

Mixtile Blade 3 offers compatibility with various operating systems, including Ubuntu, Armbian, and Debian. Upcoming support for Android and OpenWrt will open up even more possibilities.

  • Portable 2.5-inch Pico-ITX Mainboard

With a standard Pico-ITX mainboard (100 x 72 mm) and standard interfaces, Mixtile Blade 3 is designed for space-constrained embedded applications. The compact form factor meets the growing market demand and highly customized requirements of the Industrial IoT industry.

Block Diagram

Figure 3. Block diagram of Blade 3

Technical Specifications

CPURockchip Octa-core Cortex-A76/A55 SoC processor RK3588
NPUUp to 6 TOPS
Memory32 GB LPDDR4 memory
Storage256 GB eMMC storage
HDMI interfaceHDMI 2.1 output (8K @ 60 FPS or 4K @ 120 FPS)
HDMI 2.0 input (4K @ 60 FPS)
Video encoderH.264/H.265 video encoder up to 8K @ 30 FPS
Video decoderH.265/H.264/VP9 video decoder up to 8K @ 60 FPS
Camera Input4-lane MIPI-CSI
PCIe expansionMini-PCIe socket with PCIe Gen 2.1, USB 2.0 support
Storage expansion4-lane PCIe Gen 3 in U.2 port
SATA 3.0 in U.2 port, Micro-SD 3.0 flash socket
Ethernet expansionDual 2.5 Gigabit Ethernet ports
USBDual USB 3.2 Gen 1 Type-C ports, DisplayPort 1.4 A
GPIOs40-pin GPIO socket: Digital I/O, I²C, USB 2.0, TTL UART, SPI, I²S
Software supportPreloaded customized Debian 11, other Linux distributions and Android 12
PowerUSB Type-C port-1 supports USB PD 2.0 protocol (Optional: 12 V DC standard SATA power input via U.2 port)
Note: The power adapter must support PD2.0 or PD3.0 protocol. Use a USB C to USB C cable for connection.
Output Voltage5 V DC
Operating CurrentMaximum 3 A @ 20 V DC
Blade 3 dimensions2.5-inch Pico-ITX form factor, 100 x 72 mm
Blade 3 Case materialAluminium alloy, black anodized
Blade 3 case dimensions112.4mm x 89mm x 27.4mm
Operating temperature0 to +80°C

Functional Description

This section provides a detailed description to the following components of Blade 3:

  • MicroSD socket
  • Mini-PCIe socket
  • Ethernet ports
  • USB-C ports (Power port/Display port)
  • HDMI ports (HDMI Out/HDMI In)
  • U.2 connector
  • LED
  • Dip switch
Figure 4. Hardware layout of Blade 3

MicroSD Socket

The MicroSD socket accepts standard 11 mm x 15 mm Micro-SD cards with capacities up to 64 GBytes. The 4-bit data interface supports the SDMMC3.0 protocol. Blade 3 boots from eMMC flash by default and can be changed to boot from a MicroSD card.

Figure 5. MicroSD card slot on Blade 3

Mini-PCIe Socket

The module supporting configuration, including power, reset, and interrupt signals, is under software control by Core 3588. Since each module needs specific configuration definitions, check the configuration setting before connecting the module.

The mini-PCIe is a PCI card interface with a small form factor that uses a standard 52-pin mini-PCIe socket. It also contains a USB 2.0 interface. The mini-PCIe socket supports the module sizes of 3052.

Dual 2.5 Gigabit Ethernet

The IEEE 802.3 compliant Ethernet supports auto-negotiation of 10 Mbps, 100 Mbps, 1 Gbps, and 2.5 Gbps data rates in both half-duplex and full-duplex modes. The RGMII interface from the processor connects the 2.5GbE to an external PHY, RTL8125BG-CG. The RJ45 connector has some status and speed lights:

  • Green light: A valid link is established
  • Flashing light: Data is being transmitted
  • Yellow light: Link speed is 2500 Mbps
  • Off: 10/100/1000 Mbps

Power Input

Power Delivery (PD)

USB1/PD Port of Blade 3 supports USB Power Delivery 2.0. A Power Delivery controller on-board allows for a maximum power input of 20 V@3 A.

12 V DC

DC power inputs from a DC SATA power via U.2 port require 12 V@3 A.

USB-C Port

Blade 3 features two USB-C ports. There is silkscreen on PCB to indicate two USB-C ports:

  • “USB0/ADB” Type-C port near the HDMI port: supports USB-OTG and can be used for ADB debugging and firmware update.
  • “USB1/PD” Type-C port near the corner of the board: supports USB PD 2.0 for power input and does not support USB-OTG.

Both ports support USB host and DisplayPort modes. DisplayPort over USB-C enables audio/video (AV) data transfer. The ports support DisplayPort 1.4 and have a maximum resolution of 7680 x 4320@30 Hz.

Display Support

The video output processor supports the resolution from 1920 x 1080@60 Hz to 7680 x 4320@60 Hz. The default main display is HDMI.

HDMI-OUT

This port complies with HDMI 1.4, HDMI 2.1, and HDCP 2.3. It supports up to 1920 x 1080@120 Hz and 7680 x 4320@60 Hz/3840 x 2160@120 Hz resolution.

HDMI-IN

This port complies with HDMI 1.4, HDMI 2.0, and HDCP 2.3. It supports input source up to 1920 x 1080@120 Hz and 3840 x 2160@60 Hz resolution.

U.2 Connector

The U.2 interface employs a 68-pin U.2 connector with a standard SATA signal, a SATA 3.0 signal, a PCIe 3.0 x4 signal (four-lane PCIe 3.0), and 12V power input.

LED and Dip Switch

The power LED indicates the status of the power supply.

Blade 3 has an SPST four-position dip switch that can be used to determine the system booting mode.

  • When position 1 is turned to ON, Blade 3 boots from eMMC.
  • When position 2 is turned to ON, Blade 3 boots from the MicroSD card.
  • When position 3 is turned to ON, Blade 3 boots from SPI Flash.
  • When position 4 is turned to ON, Blade 3 enters MaskROM mode for firmware development.

Note:

  • Only one position can be turned to ON at a time.
  • When none of the four positions is ON, the CPU automatically searches for available boot media and boots from it. The boot order is EMMC -> SD Card -> MaskROM Mode.
Figure 6. Dip switch of Blade 3

Block Diagram

Figure 7. Block diagram of Blade 3
Figure 8. Physical dimensions of Blade 3

Connectors & Pin assignments

This section lists Blade 3 connector and pin assignments, and pin types with corresponding signal descriptions.

30-Pin connector

Pin#PinNamePinTypeInput/OutputSignal Description
1VCC_5V0PowerOutputPower supply for USB, 5 V output MAX 500 mA
2GNDPowerNAPower and signal reference ground
3USB20_HOST0_DMLVDSBIUSB20 HOST Port0 Data Minus
4I2S2_SDI_M1signalInputI2S2 data input
5USB20_HOST0_DPLVDSBIUSB20 HOST Port0 Data Plus
6I2S2_SDO_M1signalOutputI2S2 data output
7GNDPowerNAPower and signal reference ground
8I2S2_MCLK_M1signalOutputI2S2 Master clock
9I2C5_SDA_M3signalBII2C5 Bus Date
10I2S2_SCLK_M1signalBII2S2 serial clock or BCLK
11I2C5_SCL_M3signalOutputI2C5 Bus clock
12I2S2_LRCK_M1signalBII2S2 Left/Right channel clock
13GNDPowerNAPower and signal reference ground
14GNDPowerNAPower and signal reference ground
15SPI4_MISO_M2signalInputSPI4 Master input, Slave output
16CAN2_RXsignalInputCAN2 receive data
17SPI4_MOSI_M2signalOutputSPI4 Master output, Slave input
18CAN2_TXsignalOutputCAN2 transmit data
19SPI4_CLK_M2signalOutputSPI4 clock
20GNDPowerNAPower and signal reference ground
21SPI4_CS0_M2signalOutputSPI4 Chip Select 0
22GPIO0_B0signalBIGPIO bank 0 port B0
23GPIO1_A4signalBIGPIO bank 1 port A4
24SARADC_VIN7AnalogInputSAR ADC Channel 7 input
25GNDPowerNAPower and signal reference ground
26SARADC_VIN6AnalogInputSAR ADC Channel 6 input
27PWM14signalBIPulse Width Modulation 14 input or output
28GNDPowerNAPower and signal reference ground
29PWM15signalBIPulse Width Modulation 15 input or output
30VCC_3V3_S0PowerOutputPower supply  for peripheral, 3.3 V output MAX 500 mA
Table 1. 30-pin connector pin descriptions

Fan Connector

Pin#PinNamePinTypeInput/OutputSignal Description
1VCC5V_FANPowerOutputPower supply for FAN,5V output MAX 400 mA. Controlled by GPIO3_C0
2GNDPowerNAPower and signal reference ground
Table 2. Fan connector pin descriptions

Mini-PCIe

Pin#PinNamePinTypeInput/OutputSignal Description
1MINIPCIE20_WAKEN_3V3_LsignalInputWake up signal from mini-PCIe device
2VCC3V3_MINIPCIEPowerOutputPower supply for mini-PCIe device,3.3V output MAX 3A in all pins
3NCfloatNANot connected to this pin
4GNDPowerNAPower and signal reference ground
5NCfloatNANot connected to this pin
6NCfloatNANot connected to this pin
7MINIPCIE20_CLKREQN_3V3_LsignalInputPCIe2.0 Channel Reference clock request
8NCfloatNANot connected to this pin
9GNDPowerNAPower and signal reference ground
10NCfloatNANot connected to this pin
11PCIE20_2_REFCLKNLVDSOutputPCIe20 Port2 differential clock Negative
12NCfloatNANot connected to this pin
13PCIE20_2_REFCLKPLVDSOutputPCIe20 Port2 differential clock Positive
14NCfloatNANot connected to this pin
15GNDPowerNAPower and signal reference ground
16NCfloatNANot connected to this pin
17NCfloatNANot connected to this pin
18GNDPowerNAPower and signal reference ground
19NCfloatNANot connected to this pin
20W_DISABLENsignalOutputPCIE device wireless disable
21GNDPowerNAPower and signal reference ground
22MINIPCIE20_PERSTNsignalOutputPCIE device reset
23PCIE20_2_RXNLVDSInputPCIe20 receive differential Negative
24VCC3V3_MINIPCIEPowerOutputPower supply for mini-PCIe device,3.3V output MAX 3A in all pins
25PCIE20_2_RXPLVDSInputPCIe20 receive differential Positive
26GNDPowerNAPower and signal reference ground
27GNDPowerNAPower and signal reference ground
28NCfloatNANot connected to this pin
29GNDPowerNAPower and signal reference ground
30NCfloatNANot connected to this pin
31MINIPCIE20_TX_NLVDSOutputPCIe20 transmit differential  Negative
32NCfloatNANot connected to this pin
33MINIPCIE20_TX_PLVDSOutputPCIe20 transmit differential  Positive
34GNDPowerNAPower and signal reference ground
35GNDPowerNAPower and signal reference ground
36MINIPCIE_USB_DMLVDSBIUSB20 HOST Port1 Data Minus
37GNDPowerNAPower and signal reference ground
38MINIPCIE_USB_DPLVDSBIUSB20 HOST Port1 Data Plus
39VCC3V3_MINIPCIEPowerOutputPower supply for mini-PCIe device,3.3V output MAX 3A in all pins
40GNDPowerNAPower and signal reference ground
41VCC3V3_MINIPCIEPowerOutputPower supply for mini-PCIe device,3.3V output MAX 3A in all pins
42NCfloatNANot connected to this pin
43GNDPowerNAPower and signal reference ground
44NCfloatNANot connected to this pin
45NCfloatNANot connected to this pin
46NCfloatNANot connected to this pin
47NCfloatNANot connected to this pin
48NCfloatNANot connected to this pin
49NCfloatNANot connected to this pin
50GNDPowerNAPower and signal reference ground
51NCfloatNANot connected to this pin
52VCC3V3_MINIPCIEPowerOutputPower supply for mini-PCIe device,3.3V output MAX 3A in all pins
Table 3. Mini-PCIe pin descriptions

MIPI-CSI

Pin#PinNamePinTypeInput/OutputSignal Description
1GNDPowerNAPower and signal reference ground
2MIPI_CSI0_RX_D0NLVDSInputMIPI CSI0 receive differential data lane 0 Negative
3MIPI_CSI0_RX_D0PLVDSInputMIPI CSI0 receive differential data lane 0 Positive
4GNDPowerNAPower and signal reference ground
5MIPI_CSI0_RX_D1NLVDSInputMIPI CSI0 receive differential data lane 1 Negative
6MIPI_CSI0_RX_D1PLVDSInputMIPI CSI0 receive differential data lane 1 Positive
7GNDPowerNAPower and signal reference ground
8MIPI_CSI0_RX_CLK0NLVDSInputMIPI CSI0 receive differential Clock 0 Negative
9MIPI_CSI0_RX_CLK0PLVDSInputMIPI CSI0 receive differential Clock 0 Positive
10GNDPowerNAPower and signal reference ground
11MIPI_CSI0_RX_D2NLVDSInputMIPI CSI0 receive differential data lane 2 Negative
12MIPI_CSI0_RX_D2PLVDSInputMIPI CSI0 receive differential data lane 2 Positive
13GNDPowerNAPower and signal reference ground
14MIPI_CSI0_RX_D3NLVDSInputMIPI CSI0 receive differential data lane 3 Negative
15MIPI_CSI0_RX_D3PLVDSInputMIPI CSI0 receive differential data lane 3 Positive
16GNDPowerNAPower and signal reference ground
17MIPI_CAM_PWM2signalOutputPWM2 for LENS
18NCfloatNANot connected to this pin
19VCC_3V3_S0PowerOutputPower supply for sensor board,3.3V output
20MIPI_CAM_RESETNsignalOutputGPIO out for sensor reset
21NCfloatNANot connected to this pin
22MIPI_CAM_PDNsignalOutputGPIO out for sensor power down
23I2C3_SDA_M3_MIPIsignalBII2C5 Bus data
24I2C3_SCL_M3_MIPIsignalOutputI2C5 Bus clock
25GNDPowerNAPower and signal reference ground
26MIPI_CAM2_CLK_M1_3V3signalOutputCamera Master clock output
27GNDPowerNAPower and signal reference ground.
28VCC_5V0PowerOutputPower supply for sensor board, 5V output
29VCC_5V0PowerOutputPower supply for sensor board, 5V output
30VCC_5V0PowerOutputPower supply for sensor board, 5V output
Figure 4. MIPI-CSI pin descriptions

U.2

Pin#PinNamePinTypeInput/OutputSignal Description
E1PCIE30_REFCLKP_SLOTLVDSOutputRC PCIe30 differential clock Positive
E2PCIE30_REFCLKN_SLOTLVDSOutputRC PCIe30 differential clock Negative
E3VCC_3V3_S0PowerOutputPower supply for IO
E4PCIE30X4_CLKREQN_M1_LsignalOutputDM PCIe30 Channel Reference clock request
E5PCIE30X4_PERSTN_M1_LsignalInputDM PCIe30 Channel reset
E6PCIE30X4_CLKREQN_M3signalInputRC PCIe30 Channel Reference clock request
E7PCIE30_PORT1_REFCLKPLVDSInputDM PCIe30 differential clock Positive
E8PCIE30_PORT1_REFCLKNLVDSInputDM PCIe30 differential clock Negative
E9GNDPowerNAPower and signal reference ground
E10PCIE30_PORT1_TX2PLVDSOutputDM PCIe30 transmit differential  Positive
E11PCIE30_PORT1_TX2NLVDSOutputDM PCIe30 transmit differential  Negative
E12GNDPowerNAPower and signal reference ground
E13PCIE30_PORT1_RX2NLVDSInputDM PCIe30 receive differential  Negative
E14PCIE30_PORT1_RX2PLVDSInputDM PCIe30 receive differential  Positive
E15GNDPowerNAPower and signal reference ground
E16NCfloatNANot connected to this pin
E17PCIE30_PORT0_RX1PLVDSInputRC PCIe30 receive differential  Negative
E18PCIE30_PORT0_RX1NLVDSInputRC PCIe30 receive differential  Positive
E19GNDPowerNAPower and signal reference ground
E20PCIE30_PORT0_TX1NLVDSOutputRC PCIe30 transmit differential  Positive
E21PCIE30_PORT0_TX1PLVDSOutputRC PCIe30 transmit differential  Negative
E22GNDPowerNAPower and signal reference ground
E23I2C4_SCL_M0signalOutputI2C4 Bus clock
E24I2C4_SDA_M0signalBII2C4 Bus data
E25DUALPORT_EN#signalOutputGPIO for Enable dual port, default low
P1PCIE30X4_WAKEN_M1_LsignalOutputDM PCIE30 Wake up signal from RC
P2PCIE30X4_WAKEN_M3signalInputRC PCIE30 Wake up signal from DM
P3PWRDISsignalOutputGPIO for power disable to device
P4IFDETsignalInputGPIO for detect interface of device
P5GNDPowerNAPower and signal reference ground
P6GNDPowerNAPower and signal reference ground
P7NCfloatNANot connected to this pin
P8NCfloatNANot connected to this pin
P9NCfloatNANot connected to this pin
P10PRSNT#signalInputGPIO for detect device if present
P11ACTIVITY#signalInputGPIO for detect device if activity
P12GNDPowerNAPower and signal reference ground
P13U2_12VPowerInputPower supply for blade3, input 12V
P14U2_12VPowerInputPower supply for blade3, input 12V
P15U2_12VPowerInputPower supply for blade3, input 12V
S1GNDPowerNAPower and signal reference ground
S2SATA0_TXPLVDSOutputSATA30 Port0 transmit differential Positive
S3SATA0_TXNLVDSOutputSATA30 Port0 transmit differential Negative
S4GNDPowerNAPower and signal reference ground
S5SATA0_RXNLVDSInputSATA30 Port0 receive differential Positive
S6SATA0_RXPLVDSInputSATA30 Port0 receive differential Negative
S7GNDPowerNAPower and signal reference ground
S8GNDPowerNAPower and signal reference ground
S9NCfloatNANot connected to this pin
S10NCfloatNANot connected to this pin
S11GNDPowerNAPower and signal reference ground
S12NCfloatNANot connected to this pin
S13NCfloatNANot connected to this pin
S14GNDPowerNAPower and signal reference ground
S15PCIE30X4_PERSTN_M3signalOutputRC PCIe30 Channel reset
S16GNDPowerNAPower and signal reference ground
S17PCIE30_PORT1_TX3PLVDSOutputDM PCIe30 transmit differential Negative
S18PCIE30_PORT1_TX3NLVDSOutputDM PCIe30 transmit differential Positive
S19GNDPowerNAPower and signal reference ground
S20PCIE30_PORT1_RX3NLVDSInputDM PCIe30 receive differential Negative
S21PCIE30_PORT1_RX3PLVDSInputDM PCIe30 receive differential Positive
S22GNDPowerNAPower and signal reference ground
S23PCIE30_PORT0_RX0PLVDSInputRC PCIe30 receive differential  Negative
S24PCIE30_PORT0_RX0NLVDSInputRC PCIe30 receive differential  Positive
S25GNDPowerNAPower and signal reference ground
S26PCIE30_PORT0_TX0NLVDSOutputRC PCIe30 transmit differential  Negative
S27PCIE30_PORT0_TX0PLVDSOutputRC PCIe30 transmit differential  Positive
S28GNDPowerNAPower and signal reference ground
Table 5. U.2 pin descriptions

Debug

Pin#PinNamePinTypeInput/OutputSignal Description
1UART2_RX_M0_DEBUGsignalInputUART2 Receive Data for debug
2UART2_TX_M0_DEBUGsignalOutputUART2 Transmit Data for debug
3GNDsignalNAPower and signal reference ground
Table 6. UART pin descriptions

Technical Support

MIXTILE technical support team assists you with the questions you may have. Contact us with the following methods below.

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